TMS320C6414TBGLZA7

Product Summary

The TMS320C6414TBGLZA7 is a kind of fixed-point digital signal processor, which is the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C6414TBGLZA7 is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for wireless infrastructure applications. The C64x is a code-compatible member of the C6000 DSP platform. With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the device offers cost-effective solutions to high-performance DSP programming challenges. The TMS320C6414TBGLZA7 possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The device has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

Parametrics

TMS320C6414TBGLZA7 absolute maximum ratings: (1)Supply voltage ranges: CVDD: -0.5 V to 1.5 V; DVDD: -0.5 V to 4.4 V ; (2)Input voltage ranges: (except PCI), VI: -0.5 V to 4.4 V; (PCI), VIP [C6415T and C6416T only]: -0.5 V to DVDD + 0.5 V; (3)Output voltage ranges: (except PCI), VO: -0.5 V to 4.4 V; (PCI), VOP [C6415T and C6416T only]: -0.5 V to DVDD + 0.5 V; (4)Operating case temperature ranges, TC: (default and M version): 0℃ to 90℃; (A version) [A-600, A-720, A.850 only]: -40℃ to 105℃; (D version) [D.1000 only]: -40℃ to 90℃; (5)Storage temperature range, Tstg: -65℃ to 150℃.

Features

TMS320C6414TBGLZA7 features: (1)Highest-Performance Fixed-Point DSPs; (2)VelociTI.2 Extensions to VelociTI Advanced Very-Long Instruction-Word (VLIW) TMS320C64x DSP Core; (3)L1/L2 Memory Architecture; (4)Two External Memory Interfaces (EMIFs); (5)Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels); (6)Host-Port Interface (HPI); (7)Three Multichannel Buffered Serial Ports; (8)Three 32-Bit General-Purpose Timers; (9)Sixteen General-Purpose I/O (GPIO) Pins; (10)Flexible PLL Clock Generator; (11)IEEE-1149.1 (JTAG?; (12)Boundary-Scan-Compatible; (13)532-Pin Ball Grid Array (BGA) Package (GLZ/ZLZ/CLZ Suffixes), 0.8-mm Ball Pitch; (14)0.09-μm/7-Level Cu Metal Process (CMOS); (15)3.3-V I/Os, 1.1-V Internal (600 MHz); (16)3.3-V I/Os, 1.2-V Internal (720/850 MHZ, 1GHz).

Diagrams