XC6SLX9-2CSG324C

Product Summary

IC FPGA SPARTAN-6 9K 324CSGBGA

Features

Summary of Spartan-6 FPGA Features<br />
? Spartan-6 Family:<br />
? Spartan-6 LX FPGA: Logic optimized<br />
? Spartan-6 LXT FPGA: High-speed serial connectivity<br />
? Designed for low cost<br />
? Multiple efficient integrated blocks<br />
? Optimized selection of I/O standards<br />
? Staggered pads<br />
? High-volume plastic wire-bonded packages<br />
? Low static and dynamic power<br />
? 45 nm process optimized for cost and low power<br />
? Hibernate power-down mode for zero power<br />
? Suspend mode maintains state and configuration with<br />
multi-pin wake-up, control enhancement<br />
? Lower-power 1.0V core voltage (LX FPGAs, -1L only)<br />
? High performance 1.2V core voltage (LX and LXT<br />
FPGAs, -2, -3, and -3N speed grades)<br />
? Multi-voltage, multi-standard SelectIO? interface banks<br />
? Up to 1,080 Mb/s data transfer rate per differential I/O<br />
? Selectable output drive, up to 24 mA per pin<br />
? 3.3V to 1.2V I/O standards and protocols<br />
? Low-cost HSTL and SSTL memory interfaces<br />
? Hot swap compliance<br />
? Adjustable I/O slew rates to improve signal integrity<br />
? High-speed GTP serial transceivers in the LXT FPGAs<br />
? Up to 3.2 Gb/s<br />
? High-speed interfaces including: Serial ATA, Aurora,<br />
1G Ethernet, PCI Express, OBSAI, CPRI, EPON,<br />
GPON, DisplayPort, and XAUI<br />
? Integrated Endpoint block for PCI Express designs (LXT)<br />
? Low-cost PCI? technology support compatible with the<br />
33 MHz, 32- and 64-bit specification.<br />
? Efficient DSP48A1 slices<br />
? High-performance arithmetic and signal processing<br />
? Fast 18 x 18 multiplier and 48-bit accumulator<br />
? Pipelining and cascading capability<br />
? Pre-adder to assist filter applications<br />
? Integrated Memory Controller blocks<br />
? DDR, DDR2, DDR3, and LPDDR support<br />
? Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)<br />
? Multi-port bus structure with independent FIFO to reduce<br />
design timing issues<br />
? Abundant logic resources with increased logic capacity<br />
? Optional shift register or distributed RAM support<br />
? Efficient 6-input LUTs improve performance and<br />
minimize power<br />
? LUT with dual flip-flops for pipeline centric applications<br />
? Block RAM with a wide range of granularity<br />
? Fast block RAM with byte write enable<br />
? 18 Kb blocks that can be optionally programmed as two<br />
independent 9 Kb block RAMs<br />
? Clock Management Tile (CMT) for enhanced performance<br />
? Low noise, flexible clocking<br />
? Digital Clock Managers (DCMs) eliminate clock skew<br />
and duty cycle distortion<br />
? Phase-Locked Loops (PLLs) for low-jitter clocking<br />
? Frequency synthesis with simultaneous multiplication,<br />
division, and phase shifting<br />
? Sixteen low-skew global clock networks<br />
? Simplified configuration, supports low-cost standards<br />
? 2-pin auto-detect configuration<br />
? Broad third-party SPI (up to x4) and NOR flash support<br />
? Feature rich Xilinx Platform Flash with JTAG<br />
? MultiBoot support for remote upgrade with multiple<br />
bitstreams, using watchdog protection<br />
? Enhanced security for design protection<br />
? Unique Device DNA identifier for design authentication<br />
? AES bitstream encryption in the larger devices<br />
? Faster embedded processing with enhanced, low cost,<br />
MicroBlaze? soft processor<br />
? Industry-leading IP and reference designs