(Hong Kong)
Product Summary
The MT48LC4M32B2P-6G is a high-speed CMOS, dynamic andom-access memory containing 134,217,728-bits. The MT48LC4M32B2P-6G is internally configured as a quad-bank DRAM with a nchronous interface (all signals are registered on thepositive edge of the clock signal, CLK) . The MT48LC4M32B2P-6G provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
Parametrics
MT48LC4M32B2P-6G absolute maximum ratings: (1) Voltage on VDD, VDDQ Supply Relative to VSS: -1V to +4.6V; (2) Voltage on Inputs, NC or I/O Pins Relative to VSS: -1V to +4.6V; (3) Operating Temperature, TA: 0 to +70°C; (4) Storage Temperature (plastic) : -55 to +150°C; (5) Power Dissipation: 1W; (6) Operating Temperature, TA (IT) : -40 to +85°C.
Features
MT48LC4M32B2P-6G features: (1) PC100 functionality; (2) Fully synchronous; all signals registered on positive edge of system clock; (3) Internal pipelined operation; column address can be changed every clock cycle; (4) Internal banks for hiding row access/precharge; (5) Programmable burst lengths: 1, 2, 4, 8, or full page; (6) Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes; (7) Self Refresh Mode; (8) 64ms, 4,096-cycle refresh (15.6|μs/row; (9) LVTTL-compatible inputs and outputs; (10) Single +3.3V ±0.3V power supply; (11) Supports CAS latency of 1, 2, and 3.
Diagrams
