Product Summary

The Hynix HY5DU573222FP33 is a 268,435,456-bit CMOS Double Data Rate (DDR) Synchronous DRAM, ideally suited for
the point-to-point applications which requires high bandwidth. The Hynix HY5DU573222FP33 offers fully synchronous operations referenced to both rising and falling edges of the lock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK) , Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of the HY5DU573222FP33.

Parametrics

HY5DU573222FP33 absolute maximum ratings: (1) Ambient Temperature TA: 0 to 70V; (2) Storage Temperature Tstg: -55 to 125V; (2) Voltage on Any Pin relative to VSS, VIN, VOUT: -0.5 to 3.6V; (3) Voltage on VDD relative to VSS, VDD: -0.5 to 3.6V; (4) Voltage on VDDQ relative to VSS, VDDQ: -0.5 to 3.6V; (5) Output Short Circuit Current, IOS: 50mA; (6) Power Dissipation PD: 2W; (7) Soldering Temperature, Time, TSOLDER: 260°C, 10 sec.

Features

HY5DU573222FP33 features: (1) The Hynix HY5DU573222F(P) guarantee until 200MHz speed at DLL_off condition; (2) 2.5V VDD and VDDQ wide range max power supply supports; (3) All inputs and outputs are compatible with SSTL_2 interface; (4) 12mm x 12mm, 144ball FBGA with 0.8mm pin pitch; (5) Fully differential clock inputs (CK, /CK) operation; (6) Double data rate interface; (7) Source synchronous - data transaction aligned to bidirectional data strobe (DQS0 ~ DQS3) ; (8) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) ; (9) Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe; (10) Half strength and Matched Impedance driver option .

Diagrams

HY5DU573222FP33 Pin Configuration