(Hong Kong)
Product Summary
The H5RS5223CFR-11C is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The H5RS5223CFR-11C uses a double data rate architecture to achieve high-speed opreration. A single read or write access for the Hynix the H5RS5223CFR-11C consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
Parametrics
H5RS5223CFR-11C absolute maximum ratings: (1) Voltage on Vdd Supply Relative to Vss: -0.5V to +2.5V; (2) Voltage on VddQ Supply Relative to Vss: -0.5V to +2.5V; (3) Voltage on Vref and Inputs Relative to Vss: -0.5V to +2.5V; (4) Voltage on I/O Pins Relative to Vss: -0.5V to VddQ +0.5V; (5) MAX Junction Temperature, TJ: +125°C; (6) Storage Temperature (plastic) : -55°C to +150°C; (7) Power Dissipation: TBD; (8) Short Circuit Output Current: 50mA.
Features
H5RS5223CFR-11C features: (1) 2.05V/ 1.8V/ 1.5V power supply supports; (2) Single ended READ Strobe (RDQS) per byte; (3) Single ended WRITE Strobe (WDQS) per byte; (4) Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle; (5) On Die Termination; (6) Output Driver Strength adjustment by EMRS; (7) Calibrated output driver; (8) Differential clock inputs (CK and CK#) ; (9) Commands entered on each positive CK edge; (10) 8 internal banks for concurrent operation; (11) Concurrent Auto Precharge support; (12) Mirror Function with MF pin.
Diagrams
