CY7C1470BV33-200BZXI

Product Summary

The CY7C1470BV33-200BZXI is a Synchronous pipelined burst SRAM with No Bus Latency (NoBL logic, respectively. The CY7C1470BV33-200BZXI is designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV33-200BZXI is equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent read or write transitions. The CY7C1470BV33-200BZXI is pin compatible and functionally equivalent to ZBT devices.

Parametrics

CY7C1470BV33-200BZXI absolute maximum ratings: (1)Storage Temperature: –65 to +150℃; (2)Ambient Temperature with Power Applied: –55 to +125℃; (3)Supply Voltage on VDD Relative to GND: –0.5V to +4.6V; (4)Supply Voltage on VDDQ Relative to GND: –0.5V to +VDD; (5)DC to Outputs in Tri-State:–0.5V to VDDQ + 0.5V; (6)DC Input Voltage: –0.5V to VDD + 0.5V; (7)Current into Outputs (LOW): 20 mA; (8)Static Discharge Voltage: > 2001V; (9)Latch Up Current: > 200 mA.

Features

CY7C1470BV33-200BZXI features: (1)Pin-compatible and functionally equivalent to ZBT; (2)Supports 250 MHz bus operations with zero wait states, Available speed grades are 250, 200, and 167 MHz; (3)Internally self timed output buffer control to eliminate the need to use asynchronous OE; (4)Fully registered (inputs and outputs) for pipelined operation; (5)Byte Write capability; (6)Single 3.3 V power supply; (7)3.3 V/2.5 V IO power supply; (8)Fast clock-to-output time, 3.0 ns (for 250 MHz device); (9)Clock Enable (CEN) pin to suspend operation; (10)Synchronous self timed writes; (11)CY7C1470BV33, CY7C1472BV33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1474BV33 available in Pb-free and non-Pb-free 209-ball FBGA package; (12)IEEE 1149.1 JTAG Boundary Scan compatible; (13) Burst capability—linear or interleaved burst order; (14)ZZ Sleep Mode option and Stop Clock option.

Diagrams