HY5DU573222FP-33

Product Summary

The HY5DU573222FP-33 is a kind of 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM. The device is suitable for the point-to-point applications which requires high bandwidth. The HY5DU573222FP-33 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.

Parametrics

HY5DU573222FP-33 absolute maximum ratings: (1)Ambient Temperature, TA: 0 to 70℃; (2)Storage Temperature, TSTG: -55 to 125℃; (3)Voltage on Any Pin relative to VSS, VIN, VOUT: -0.5 to 3.6 V; (4)Voltage on VDD relative to VSS, VDD: -0.5 to 3.6 V; (5)Voltage on VDDQ relative to VSS, VDDQ: -0.5 to 3.6 V; (6)Output Short Circuit Current, IOS: 50 mA; (7)Power Dissipation, PD: 2 W.

Features

HY5DU573222FP-33 features: (1)The Hynix HY5DU573222F(P) guarantee until 200MHz speed at DLL_off condition; (2)2.5V VDD and VDDQ wide range max power supply supports; (3)All inputs and outputs are compatible with SSTL_2 interface; (4)12mm x 12mm, 144ball FBGA with 0.8mm pin pitch; (5)Fully differential clock inputs (CK, /CK) operation; (6)Double data rate interface; (7)Source synchronous - data transaction aligned to bidirectional data strobe (DQS0 ~ DQS3); (8)Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe; (9)All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock; (10)Write mask byte controls by DM (DM0 ~ DM3); (11)Programmable /CAS Latency 5 / 4 / 3 supported; (12)Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode; (13)Internal 4 bank operations with single pulsed /RAS; (14)tRAS Lock-Out function supported; (15)Auto refresh and self refresh supported; (16)4096 refresh cycles / 32ms; (17)Half strength and Matched Impedance driver option.

Diagrams